Qualcomm MSM8994 CPU clock tree

clock-cpu-8994 is a device that represents the MSM8994 CPU subsystem
clock tree. It lists the various power supplies that need to be scaled when
the clocks are scaled and also other HW specific parameters like fmax tables,
avs settings table, etc.

Required properties:
- compatible:		Must be one of "qcom,clock-cpu-8994" or
			"qcom,clock-cpu-8994-v2"
- reg:			Pairs of physical base addresses and region sizes of
			memory mapped registers.
- reg-names:		Names of the bases for the above registers. Expected
			bases are:
			"c0_pll", "c1_pll", "cci_pll", "c0_mux",
			"c1_mux", "cci_mux"
- vdd-a53-supply:	The regulator powering the A53 cluster
- vdd-a57-supply:	The regulator powering the A57 cluster
- vdd-cci-supply:	The regulator powering the CCI cluster
- vdd-pll-supply:	The regulator powering the cluster PLLs
- qcom,a5X-speedbinY-vZ:
			A table of CPU frequency (Hz) to voltage (corner)
			mapping that represents the max frequency possible
			for each supported voltage level for a CPU. 'Y' is
			the speed bin into which the device falls into - a
			bin will have unique frequency-voltage relationships.
			'Z' is the characterization version, implying that
			characterization (deciding what speed bin a device
			falls into) methods and/or encoding may change. The
			values 'Y' and 'Z' are read from efuse registers, and
			the right table is picked from multiple possible tables.
			 'X' is 3 or 7 depending on whether the table is for the
			A53 or A57 cluster.
- qcom,cci-speedbinY-vZ:
			Similar to the qcom,a5X-speedbinY-vZ property described
			above, except this frequency to voltage table is applied
			to the clock for the CCI.
Example:
	clock_cpu: qcom,cpu-clock-8994@f9015000 {
		compatible = "qcom,cpu-clock-8994";
		reg = <0xf9015000 0x1000>,
		      <0xf9016000 0x1000>,
		      <0xf9011000 0x1000>,
		      <0xf900d000 0x1000>,
		      <0xf900f000 0x1000>,
		      <0xf9112000 0x1000>;
		reg-names = "c0_pll", "c1_pll", "cci_pll", "c0_mux", "c1_mux", "cci_mux";
		vdd-a53-supply = <&apc0_vreg_corner>;
		vdd-a57-supply = <&apc1_vreg_corner>;
		qcom,a53-speedbin0-v0 =
			<         0 0>,
			< 384000000 1>,
			< 787200000 2>,
			<1286400000 3>;
		qcom,a57-speedbin0-v0 =
			<         0 0>,
			< 384000000 1>,
			< 787200000 2>,
			<1785600000 3>;
		qcom,cci-speedbin0-v0 =
			<         0 0>,
			< 150000000 1>,
			< 300000000 2>,
			< 600000000 3>;
		clock-names = "xo", "aux_clk";
		clocks = <&clock_rpm clk_cxo_clk_src>,
			 <&clock_gcc clk_gpll0_ao>;
		#clock-cells = <1>;
	};


