Qualcomm Technologies Memory Accelerator

Memory accelerator configures the power-mode (corner) for the
accelerator.

Required properties:
- compatible:			Must be "qcom,mem-acc-regulator"
- regulator-name:		A string used to describe the regulator
- regulator-min-microvolt:	Minimum corner value as min constraint, which
				should be 1 for SVS corner
- regulator-max-microvolt:	Maximum corner value as max constraint, which
				should be 4 for SUPER_TURBO or 3 for TURBO
- qcom,corner-acc-map		Array which maps the APC (application processor)
				corner value to the accelerator corner.
				[0] maps APC SVS corner (1) to accelerator SVS corner
				[1] maps APC NOMINAL corner (2) to accelerator NOMINAL corner
				[2] maps APC TURBO corner (3) to accelerator TURBO corner

Optional properties:
- reg:				Register addresses for acc-en and acc-sel-l1
				acc-sel-l2 control and MEM ACC eFuse address.
- reg-names:			Register names. Must be "acc-sel-l1",
				"acc-sel-l2", "acc-en", "efuse_addr".
				A given mem-acc-regulator driver must have "acc-sel-l1" or
				"acc-sel-l2" reg-names property and related register address
				property.
- qcom,acc-en-bit-pos		Array which specifies bit positions in the
				'acc-en' register. Setting these bits forces the
				the acclerator to use the corner value specified
				in the 'acc-sel-l1' and 'acc-sel-l2' register.
- qcom,acc-sel-l1-bit-pos	Array which specifies bit positions in the
				'acc-sel-l1' register. Each element in this array
				is the LSB of a 2-bit value. This 2-bit value
				specifies the corner value used by the
				accelerator for L1 cache.
- qcom,acc-sel-l2-bit-pos	Array which specifies bit positions in the
				'acc-sel-l2' register. Each element in this array
				is the LSB of a 2-bit value. This 2-bit value
				specifies the corner value used by the
				accelerator for L2 cache.
- qcom,l1-config-skip-fuse-sel:	Array of 5 elements to indicate where to read the bits, what value to
				compare with in order to decide whether to
				skip configuring the L1 accelerator or not while changing the APC corner
				and method to read fuse row, using SCM to read or read register directly.
				The 5 elements with index [0..4] are:
				  [0] => the fuse row number of the selector
				  [1] => LSB bit position of the bits
				  [2] => number of bits
				  [3] => the value to select skip L1 config logic
				  [4] => fuse reading method, 0 for direct reading or 1 for SCM reading
				When the value of the fuse bits specified by first 3 elements equals to
				the value in 4th element, L1 accelerator
				configuration logic is skipped. Otherwise, the original configuration sent
				from corner map should be applied. If the 5th element is 0, read the fuse row
				from register directly. Otherwise, read it through SCM.

mem_acc_vreg_corner: regulator@fd4aa044 {
	compatible = "qcom,mem-acc-regulator";
	reg = <0xfd4aa048 0x1>, <0xfd4aa044 0x1>, <0xfd4af000 0x1>, <0x58000 0x1000>;
	reg-names = "acc-en", "acc-sel-l1" , "acc-sel-l2", "efuse_addr";
	regulator-name = "mem_acc_corner";
	regulator-min-microvolt = <1>;
	regulator-max-microvolt = <3>;

	qcom,acc-en-bit-pos = <0>;
	qcom,acc-sel-l1-bit-pos = <0>;
	qcom,acc-sel-l2-bit-pos = <0>;
	qcom,corner-acc-map = <0 1 3>;
	qcom,l1-config-skip-fuse-sel = <0 52 1 1 0>;
};
